The present invention relates to an electrically erasable programmable floating gate memory, such as flash memory or electrically erasable programmable read only memory (EEPROM) for both memory and programmable logic application. More specifically, the present invention relates to a method and structure to detect negative voltages to improve programming of a memory cell.
Many memory cell arrays, such as flash memory cells, use Fowler-Nordheim (F-N) tunneling mechanisms to program and erase the memory cells. F-N tunneling occurs when a large voltage differential exists between the control gate terminal and a source/drain terminal of a memory cell. The large voltage differential establishes an electrical field in the tunnel oxide region of the memory cell. This electrical field promotes the acquisition of electrons by or distribution of electrons from the floating gate of the memory cell, depending on the direction of the voltage differential. When the voltage (e.g., +15 Volts) applied to the control gate terminal is much larger than the voltage (e.g., 0 Volts) applied to the source/drain terminal, electrons are drawn into the floating gate. When the voltage (e.g., 0 Volts) applied to the control gate terminal is much smaller than the voltage (e.g., +15 Volts) applied to the source/drain terminal, electrons are expelled from the floating gate.
Some F-N tunneling schemes use positive and negative voltages to reduce the stress on chip elements. In these cases, the large voltage differential is created by having a positive voltage on one terminal of the memory cell and a negative voltage on another terminal. Thus, to draw electrons into the floating gate, a positive voltage (e.g., +5 Volts) is applied to the control gate terminal of the memory cell and a negative voltage (e.g., xe2x88x928 Volts) is applied to the source/drain terminal. Also, to remove electrons from the floating gate, a negative voltage (e.g., xe2x88x928 Volts) is applied to the control gate terminal of the memory cell and a positive voltage (e.g., +5 Volts) is applied to the source/drain terminal.
Both a VCC supply voltage (e.g., 3.3 Volts) and ground (0 Volts) voltages are readily available to any circuit on a chip. A charge pump must be used for voltages greater than the VCC supply voltage or less than ground. Thus, charge pumps are needed to achieve the voltage differential required for an F-N tunneling operation.
A negative charge pump produces a negative supply voltage, VNN. The VNN negative supply voltage is the negative voltage used for the F-N tunneling operation. The negative charge pump operates by gradually decreasing (pumping down) the VNN negative supply voltage from an initial voltage of ground to the desired negative voltage.
A positive charge pump produces a positive supply voltage, VPP. The VPP positive supply voltage is the positive voltage used for the F-N tunneling operation. The positive charge pump operates by gradually increasing (pumping up) the VPP positive supply voltage from an initial voltage of ground to the desired positive voltage. The requirement of pumping these supply voltages causes a delay before these supply voltages reach their final desired voltages.
In a conventional F-N tunneling operation, the time between the initiation of pumping of the negative charge pump and the initiation of pumping between the positive charge pump may not be optimized. As a result, a high negative voltage applied to the control gate and a high positive voltage applied to the drain or source region to remove electrons from the floating gate may cause an electrical field spike in the tunnel oxide. This electrical field spike can induce xe2x80x9celectron trappingxe2x80x9d in the tunnel oxide, wherein electrons from the F-N tunneling operation become trapped in the tunnel oxide adjacent to the top surface of the substrate of a memory cell. Electron trapping thus reduces the effectiveness of the F-N tunneling operation by reducing the number of electrons that pass through the tunnel oxide of the memory cell during the F-N operation. Over many repetitions of the F-N operation, increasing numbers of electrons become trapped in the tunnel oxide of the memory cell. The amount of time a memory cell must undergo an F-N tunneling operation increases with the number of electrons trapped in the tunnel oxide of the memory cell. Each memory cell undergoing F-N tunneling in an array is affected by electron trapping. As a result, electron trapping causes an entire memory cell to undergo increasingly longer durations of F-N tunneling operations over time. Therefore, a need arises for a way to minimize fluctuations in the electrical field during programming of the memory cells.
The present invention provides a tunable circuit for optimizing an electrical field generated by the F-N tunneling operation.
To optimize the electrical field, the charging of the positive charge pump is begun after the charging of the negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from a negative charge pump. A node within the resistor chain is compared to a second reference voltage using a comparator. In this way, the node within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected.
The output signal of the comparator changes state when the voltage at the node within the resistor chain decreases below the second reference voltage. This output signal triggers the charging of a positive charge pump. Additional resistance is added to or removed from the resistor chain via metal options or switches. By changing the resistance within the resistor chain, the positive charge pumping may be initiated at varying negative voltages.
Thus, the tunable circuit of the present invention provides a way to trip the charging of a positive charge pump based on a given voltage level of a negative charge pump during an F-N tunneling operation, thereby maintaining a constant electrical field during programming of the memory cells.